1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a method for forming a gate using a gate layout with a tab attached to a gate in an edge portion of an active region.
2. Description of the Related Art
As high integration of a DRAM device progresses more rapidly, the pattern of implementing a device becomes more miniaturized. Since a design rule is drastically reduced, degradation of transistor characteristic becomes significant. As a result of high integration, gate length of a transistor, that is, line width of a gate line, becomes smaller. However, it is important that the reliability of the transistor not be reduced.
As gate length is reduced in a transistor, punch-through by hot electrons produced from an edge portion of an active region, that is, HEIP (Hot-Electron Induced Punch-through) becomes a factor in degradation of device characteristics. A Shallow Trench Isolation (STI) process is adopted and formation of a major current path by field crowding effect in a gate region passing through an edge portion of an active region becomes a reliability problem like HEIP.
Though there are many methods to overcome degradation of device characteristics, the method for simply changing a layout of a gate reduces HEIP of a PMOS transistor. There is considered the method of stretching gate length selectively in a gate edge portion with gate channel edge with a tab attached. That is, there is being given some consideration to solving the related problem of HEIP by a gate with a tab attached to distribute an electric current path.
FIGS. 1 through 3 are schematic views illustrating a conventional gate layout of a semiconductor device.
Referring to FIG. 1, a conventional gate is formed of a line crossing over a rectangular active region 10. Referring to FIG. 2, there are more than two gates 20 crossing over the active region 10 in the form of lines. As shown in FIG. 2, a tab is attached to the overlapping gate 20 in the edge portion of the active region 10 to solve the problem of HEIP.
As shown in FIG. 3, when the distance between the gates 20 is very small, the gates 20 can make contact via tabs 25. That is, when patterning an actual gate 40 on a wafer using a gate layout shown in FIG. 2, bridge portion 45 between gates 40 can be produced. Consequently, an additional process for removing or cutting the joint portion between gates 40 is required. In the process of removing the bridge portion 45 between the gates 40, the tab becomes too small so that the effect of stretching the length of gate 40 in preventing the HEIP is reduced. In essence, when the length of gate 20 in PMOS transistor shown in FIG. 2 is designed to be about 350 nm, the tab 25 attached to the gate 20 is a rectangular pattern with about 120 nm in length and width. Since designing the spacing between gates 20 is roughly 270 nm, the spacing between tabs 25 is only 30 nm.
As shown in FIG. 2, when an etch-mask pattern for patterning gates using a photomask formed with a layout in the photoetching process, that is, photoresist pattern is formed and photoresist pattern that corresponds to the tab 25 reduces to the width of about 96 nm by photoresist shrinkage when an ArF light source is used during an exposing process. However, the spacing 30 remains very narrow compared to the exposure limitation. Accordingly, when patterning the actual gate 40 of FIG. 3 using the etch mask, the space of the gate 40 is connected as shown in FIG. 3.
The process of removing the bridge portion 45, that is, the cutting process, needs to be carried out to remove about 100-nm tab and finally the width of the tab is reduced. Accordingly, after the cutting process, the remaining tab has a width of about 20 nm. Considering the width of the gate 20 in the layout is designed to be 350 nm, the tab is formed with a width of 20 nm so that the actual effect of stretching the length of the gate 40 is greatly reduced. Accordingly, in spite of tab attachment in the layout, the gate 40 after actual gate patterning has very little of the effect of tab attachment. Therefore, prevention of HEIP by tab attachment is degraded.